1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to forming a p-channel transistor having source and drain regions implanted with multiple energy/dose impurity combinations to form a graded junction.
2. Description of the Related Art
Because of the increased desire to build faster and more complex integrated circuits, it has become necessary to reduce the transistor threshold voltage, V.sub.T. Several factors contribute to V.sub.T, one of which is the effective channel length ("L.sub.eff ") of the transistor. The initial distance between the source-side junction and the drain-side junction of a transistor is often referred to as the physical channel length, L. However, after implantation and subsequent diffusion of the junctions, the electrical distance between junctions becomes less than the physical channel length and is often referred to as the effective channel length, L.sub.eff. In VLSI designs, as the physical channel length decreases, so too must L.sub.eff. Decreasing L.sub.eff reduces the distance between the depletion regions associated with the source and drain of a transistor. As a result, less gate charge is required to invert the channel of a transistor having a short L.sub.eff. Accordingly, reducing L, and hence L.sub.eff, can lead to a reduction in the threshold voltage of a transistor. Consequently, the switching speed of the logic gates of an integrated circuit employing transistors with reduced L.sub.eff is faster, allowing the integrated circuit to quickly transition between logic states (i.e., operate at high frequencies). Minimizing L also improves the speed of integrated circuits including a large number of individual transistors because the larger drain current associated with a short channel length can drive the adjoining transistors into saturation more quickly. Also, the smaller L has less parasitic capacitance. Minimizing L is, therefore, desirable from a device operation standpoint.
In addition, minimizing L is desirable from a manufacturing perspective because a smaller area of silicon is required to manufacture a transistor having a smaller length. By minimizing the area required for a given transistor, the number of transistors available for a given area of silicon increases, with a corresponding increase in the circuit complexity that can be achieved on the given area of silicon. As layout densities increase, however, the problems associated with fabrication of transistors are exacerbated. Although n-channel devices are particularly sensitive to so-called short-channel effects ("SCE"), SCE also becomes a predominant problem in p-channel devices whenever L.sub.eff drops below approximately 0.8 .mu.m.
A problem related to SCE and the subthreshold currents associated therewith is the problem of hot-carrier effects ("HCE"). HCE are phenomena by which the kinetic energy of the carriers (holes or electrons) is increased as they are accelerated through large potential gradients and subsequently become trapped within the gate oxide. The greatest potential gradient, often referred to as the maximum electric field ("E.sub.m "), occurs near the drain during saturated operation. More specifically, the electric field is predominant at the lateral junction of the drain adjacent the channel. The electric field at the drain primarily causes electrons in the channel to gain kinetic energy and become "hot". As hot electrons travel to the drain, they lose their energy by a process called impact ionization. Impact ionization serves to generate electron-hole pairs, wherein the pairs migrate to and become injected within the gate dielectric near the drain junction. Traps within the gate dielectric generally become electron traps, even if they are partially filled with holes. As a result, there is a net negative charge density in the gate dielectric. The trapped charge accumulates with time, resulting in a positive threshold shift in an NMOS transistor, or a negative threshold shift in a PMOS transistor.
To overcome the problems of sub-threshold current and threshold shift resulting from SCE and HCE, an alternative drain structure known as a lightly doped drain ("LDD") is commonly used. The purpose of the LDD is to absorb some of the potential into the drain and thus reduce E.sub.m. Fabrication of a conventional LDD structure is depicted in FIGS. 1A-1C. A light concentration of dopant 16 is implanted into semiconductor substrate 10 self-aligned to gate conductor 14 (FIG. 1A). The light implant dose serves to produce a lightly doped section 18 within the junction at the gate edge near the channel 12. Sidewall spacers 20 are then formed adjacent the sidewalls of gate conductor 14, followed by a heavier dopant implant 22 self-aligned to the sidewall spacers (FIG. 1B). The heavy implant dose is spaced from the channel a distance dictated by the thickness of the sidewall spacers. The heavy implant dose forms the source/drain implant 24 placed within the junction laterally outside the LDD area. As a result, a dopant gradient (i.e., "graded junction") occurs at the interface between the source and channel as well as between the drain and channel. Following anneal (FIG. 1C), ions implanted to form LDD 18 may diffuse into channel region 12, thus further decreasing L.sub.eff. Consequently, less bias overall must be applied to the gate to invert the channel across its full width, a phenomenon known as V.sub.T roll-off. If L.sub.eff is decreased to a great enough extent, V.sub.T may be lowered sufficiently to allow a subthreshold current to flow through the channel even when no external voltage is applied, so that the device is always "on". This problem is especially acute with boron ions used to form LDD and source/drain regions in PMOSFETs due to the high diffusivity of boron.
In an attempt to counteract the high diffusivity of boron, PMOSFETs may be formed using the method depicted in FIGS. 2A-2C. First spacers 36 may be formed adjacent opposed sidewalls of gate conductor 34 (FIG. 2A). A light concentration of dopant 38 may then be implanted into semiconductor substrate 30 self-aligned to the first spacers to produce LDD 40. Second sidewall spacers 42 may then be formed adjacent first sidewall spacers 36, followed by a heavier dopant implant 44 self-aligned to the second sidewall spacers to form the source/drain implant 46 (FIG. 2B). The thickness of first spacer 36 may be sufficient to prevent diffusion of implanted boron ions 40 into channel region 32 during anneal, as shown in FIG. 2C.
As the gate width decreases into the sub-quarter-micron range, a concurrent reduction in spacer width is desirable to maintain proper device scaling. Narrow spacer fabrication, however, is at present difficult, and, depending upon processing conditions, the widths of narrow spacers may vary considerably between and even across semiconductor wafers. This may in turn lead to variability in L.sub.eff such that V.sub.T exhibits a wide range of values across a semiconductor device. It would therefore be desirable to fabricate sub-quarter-micron MOSFETs in which spacer thickness, and thus L.sub.eff,, is more easily controlled so that V.sub.T roll-off is minimized or eliminated.